Title :
A fast minimum cost flow algorithm for VLSI layout compaction
Author :
Arungsrisangchai, Ltthichai ; Shigehiro, Yuji ; Shirakawa, Lsao ; Takahashi, Hiromitsu
Author_Institution :
Dept. of Electron. Eng., King Mongkut´´s Inst. of Technol., Bangkok, Thailand
Abstract :
Since the layout compaction problem is dual to the minimum cost flow problem, flow algorithms can be applicable to the layout compaction. In this paper, an existing flow algorithm is investigated in terms of the layout compaction, and a fast flow algorithm is devised on the basis of the primal-dual method. Experimental results show that the proposed algorithm is the fastest dedicatedly for the compaction problem
Keywords :
VLSI; application specific integrated circuits; circuit layout CAD; directed graphs; integrated circuit layout; VLSI layout compaction; compaction problem; fast flow algorithm; minimum cost flow algorithm; primal-dual method; Compaction; Computer science; Constraint optimization; Constraint theory; Costs; Information systems; Linear programming; Productivity; Systems engineering and theory; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621455
