Title :
A new optimization cost model for VLSI standard cell placement
Author :
Cheung, P.Y.S. ; Yeung, C.S.K. ; Tse, S.K. ; Yuen, C.K. ; Ko, W.L.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong
Abstract :
In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results show that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool
Keywords :
VLSI; cellular arrays; circuit layout CAD; circuit optimisation; logic CAD; network routing; simulated annealing; VLSI; cost model; detailed routing phase; layout area reduction; optimization cost model; simulated annealing; standard cell placement; Cost function; Joining processes; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621464
