Title :
A compiled-code parallel pattern logic simulator with inertial delay model
Author :
Huang, Kuo Chan ; Lee, Chung Len ; Chen, Jwu E.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating with inertial functions, to execute event-cancelling operation for gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it surpasses significantly over the conventional time wheel event-driven simulator in the simulation speed. In addition, it is also found that, significant percentage (27%) of hazards should be eliminated when only the transport delay is considered in the simulation
Keywords :
circuit layout CAD; delays; logic CAD; logic design; compiled code parallel pattern logic simulator; inertial delay model; logic gate; potential-change frame; transport delay; Circuit simulation; Circuit testing; Discrete event simulation; Hazards; Logic gates; Propagation delay; Semiconductor device modeling; Switches; Timing; Wheels;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621470
