• DocumentCode
    3584614
  • Title

    Hierarchical synchronization scheme using self-timed mesochronous interconnections

  • Author

    Kim, Seokjin ; Sridhar, Ramalingam

  • Author_Institution
    Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
  • Volume
    3
  • fYear
    1997
  • Firstpage
    1824
  • Abstract
    As technology advances, keeping purely synchronous clocking scheme for a large, high-speed design becomes increasingly difficult, mainly due to the difficulties in controlling interconnection delays. This paper presents a two-level synchronization scheme. A complex system is divided into several independently clocked modules. Communication between the modules is achieved by an interconnection scheme called “self-timed mesochronous interconnection”. The delay independence of the scheme eliminates the need for judicious control of the clock distribution network and of data interconnects. Experiments on two structures, unidirectional and signal joining cases, have shown that the scheme operates regardless of the amount of clock skew and interconnection delay between modules
  • Keywords
    clocks; delays; digital integrated circuits; integrated circuit design; integrated circuit interconnections; synchronisation; clock distribution network; hierarchical synchronization scheme; high-speed design; independently clocked modules; interconnection delays; self-timed mesochronous interconnections; signal joining structure; two-level synchronization scheme; unidirectional structure; Clocks; Communication system control; Delay effects; Design optimization; Digital communication; Flip-flops; Integrated circuit interconnections; Process design; Synchronization; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.621501
  • Filename
    621501