Delay constrained optimization by simultaneous fanout tree construction, buffer insertion/sizing and gate sizing

We present a novel algorithm for delay constrained optimization of combinational logic, extending the state-of-the-art sizing algorithm based on Lagrangian relaxation. We tightly integrate fanout tree construction, buffer insertion/sizing and gate sizing, thereby achieving more optimization than if they were performed independently. We consider the network in its entirety, thereby taking full advantage of the slacks available on the noncritical paths. We have implemented our algorithm and experimented with it on ISCAS-89 benchmark circuits; the results demonstrate that it is effective as well as fast