Application-based, transistor-level full-chip power analysis for 700 MHz PowerPCTM microprocessor

A chip-level transient power analysis methodology for the 700 MHz PowerPC^TM microprocessor has been presented. Transistor-level simulation is used for best accuracy, while input vectors are gathered at the architectural level from certain applications. The IVP is used to describe the sequence of instructions that drive the applications under architecture-specific constraints. The generated cycle-based logic behaviors are then mapped to the timing-based input vectors to regenerate the timing relationship between signals. Algorithms have been presented for simulating the transient power. This methodology can simulate the blocks in a hierarchical manner, while the accuracy is preserved. By fetching the logic values from the AET file, the simulation can start at any user specified cycle to handle RTX state preload and to avoid simulation time waste at the initialization period. Three simulation cases have been studied, including a large custom array, an FPU, and the full chip including IR-drop analysis. This transient power analysis methodology has been successfully employed along the course of PowerPC^TM development for the power-aware design of the next-generation microprocessor