DocumentCode :
358528
Title :
On test application time and defect detection capabilities of test sets for scan designs
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
2000
fDate :
2000
Firstpage :
395
Lastpage :
400
Abstract :
The test application time of test sets for scan designs can be reduced (without reducing the fault coverage) by removing some scan operations, and increasing the lengths of the primary input sequences applied between scan operations. In this paper, we study the effects of such a compaction procedure on the ability of a test set to detect defects. Defect detection is measured by the number of times the test set detects each stuck-at fault, which was shown to be related to the defect coverage of the test set. We also propose a compaction procedure that affects the numbers of detections of stuck-at faults in a controlled way
Keywords :
logic design; logic testing; compaction procedure; defect detection capabilities; scan designs; stuck-at fault; stuck-at faults; test application time; test sets; Application software; Circuit faults; Circuit testing; Cities and towns; Clocks; Compaction; Delay; Design engineering; Electrical fault detection; Fault detection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-7695-0801-4
Type :
conf
DOI :
10.1109/ICCD.2000.878314
Filename :
878314
Link To Document :
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