A scalable high-performance DMA architecture for DSP applications

As frequency and processing capabilities of today´s Digital Signal Processors (DSPs) are increasing, so is the needed data rate to fully utilize the available processing bandwidth. Moreover, high-end applications may require multiple DSP´s on a single chip, further pushing the data rate requirements. There are varying external devices with which the processors may wish to communicate concurrently. A `plug and play´ like approach for external devices and a scalable high-performance multi-processor data rate solution would be highly desirable. In this paper, a scalable, high performance Direct Memory Access (DMA) architecture for all on-chip and off-chip data communication between multiple processors and various external devices is proposed. This architecture has been implemented on Texas Instruments TMS320C6211 C6x DSP