DocumentCode
358534
Title
Advanced wiring RC timing design techniques for logic LSIs in gigahertz era and beyond
Author
Ito, Yuko ; Isomura, Satoru ; Hiyama, Toru ; Nojiri, Kazunobu ; Maeda, Eijiro
Author_Institution
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fYear
2000
fDate
2000
Firstpage
556
Lastpage
558
Abstract
In this paper, we describe an advanced wiring RC timing design techniques for the gigahertz era. Our new technique of wiring capacitance extraction makes it possible to calculate more than 1 M nets within 3 hours as accurately as carrying out net-by-net 3-D simulations. Furthermore, we introduced the timing window for estimating crosstalk effects on delay time so as to distinguish harmful nets from harmless nets and reduce surplus design guard-bands
Keywords
circuit layout CAD; large scale integration; logic design; timing; wiring; 3-D simulations; advanced wiring RC timing design; capacitance extraction; crosstalk effects; logic LSIs; Capacitance; Crosstalk; Delay effects; Delay estimation; Large scale integration; Logic design; Logic devices; Power supplies; Timing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-0801-4
Type
conf
DOI
10.1109/ICCD.2000.878340
Filename
878340
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