Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications

In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices/vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input, multiple-output (MIMO) systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware implementation of the algorithm is achieved via a highly pipelined, partly systolic FPGA architecture. We verify the algorithmic accuracy of the architecture, which is scalable in terms of the order of the input matrices, through FPGA-in-the-loop hardware co-simulations. Results are presented to demonstrate the accuracy and capability of the architecture.