Title :
Hardware/software co-design architecture for Blokus Duo solver
Author :
Sugimoto, Naru ; Amano, Hideharu
Author_Institution :
Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan
Abstract :
This paper presents a software and hardware design of an FPGA-based Blokus Duo solver. We used Embedded system called ZYNQ-7000 All Programmable SoC to implement the solver. By combining hardware with software, efficient acceleration is performed. Our system searches a game tree by using the miniMax algorithm with alpha-beta pruning. The implemented solver works at 75MHz with Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 on the Digilent ZedBoard. It can search states after three moves in most cases.
Keywords :
computer games; embedded systems; field programmable gate arrays; hardware-software codesign; minimax techniques; system-on-chip; Blokus Duo solver; Digilent ZedBoard; FPGA; Xilinx Zynq-7000 AP SoC XC7Z020-CLG484; ZYNQ-7000 all programmable SoC; alpha-beta pruning; embedded system; frequency 75 MHz; game tree; hardware/software co-design architecture; minimax algorithm; Artificial intelligence; Computer architecture; Field programmable gate arrays; Games; Hardware; Software; System-on-chip;
Conference_Titel :
Field-Programmable Technology (FPT), 2014 International Conference on
Print_ISBN :
978-1-4799-6244-0
DOI :
10.1109/FPT.2014.7082820
