Efficient VLSI architecture for FIR filter using DA-RNS

In this paper, an efficient multiplier less finite impulse response (FIR) filter architecture based on distributed arithmetic (DA) using high speed residue number system (RNS) is presented. The proposed architecture uses RNS and parallel DA to increase the speed of the system. The proposed architecture is coded in VHDL and synthesized using Synopsys Design Compiler using SAED 90nm CMOS library to calculate area and delay. Synthesis results show that, the proposed structure using DA-RNS has 77.93% less area-delay-product (ADP) than the design proposed by Chan Hua Vun.