SynDEx-Mix: A hardware/software partitioning CAD tool

Real-time embedded applications require high computational performances. Mixed Architectures which contain programmable and reconfigurable parts may be the solution to meet this computational requirement. FPGA vendors start to sell such mixed architectures. But the implementation of an algorithm on these architectures lead to a huge number of possible implementations that had to be explored in order to reach real-time and resource minimization. Therefore, the use of a rapid prototyping methodology is required to automate the partitioning task and the code generation in order to reduce time to market. Consequently there is a great need for dedicated tools, covering simultaneously both programmable and reconfigurable components in a unified framework. Architecture Algorithm Adequation (AAA) is one of those rapid prototyping methodologies implemented in two differents tools targeting programmables components on the one hand, and reconfigurable components on the other hand. Since AAA does not support mixed architectures, this paper presents an extension of this methodology, and a new tool that couples SynDEx for programmable components and SynDEx-IC for reconfigurable components. This tool is called SynDEx-Mix.