A Case Study of Multiprocessor Bugs Found Using RIS Generators and Memory Usage Techniques

Author

Venkatesan, Deepak ; Nagarajan, Pradeep

Author_Institution

Syst. & Software Group, ARM Embedded Technol. Pvt. Ltd., Bangalore, India

fYear

2014

Firstpage

4

Lastpage

9

Abstract

Random Instruction Sequence (RIS) Generators are widely used for functional verification of processors. In the case of multiprocessor systems, these RIS tools can be used to generate instructions that act upon data shared between the multiple processors in the system. In addition to the random instruction sequences, addition of semi-directed functional sequences and deterministic instruction patterns in the tool -- orthogonal to the randomly generated instructions increase the chances of reaching the desired corner cases faster. Using carefully crafted address reuse and virtual memory mapping data inconsistency issues and arbitration bugs in the processors can be hit faster. This paper presents a case study of two bugs which were found in cache coherent multiprocessor systems using a RIS tool, and semi-directed sequences.

Keywords

cache storage; computer debugging; multiprocessing systems; virtual storage; RIS generators; RIS tools; arbitration bugs; cache coherent multiprocessor systems; data inconsistency; deterministic instruction patterns; functional verification; memory usage techniques; multiprocessor bugs; random instruction sequence; virtual memory; Algorithms; Coherence; Computer bugs; Generators; Memory management; Multiprocessing systems; Program processors; RIS generator; cache invalidation request; multiprocessor verification; random instruction sequence; virtual address;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification Workshop (MTV), 2014 15th International

ISSN

1550-4093

Type

conf

DOI

10.1109/MTV.2014.28

Filename

7087225