Optimized Simulation Acceleration with Partial Testbench Evaluation

With growing adoption of the simulation acceleration technology for early functional verification of complex System-on-chip (SoC) designs, high level test benches contain substantial number of calls for debug and design state manipulation, to increase functional coverage. Ever increasing size and complexity of digital designs make these calls compute and IO intensive, requiring large software pre-processing time to prepare data suitable for feeding into the hardware accelerator. On the hardware side, growing design sizes are easily handled by parallelism inherently present in hardware accelerators with reconfigurable architecture, but it is often not trivial to speed up complex software test benches via parallel processing. In this paper, we present a novel methodology which enhances the performance of the system significantly by moving the software pre-processing time to an offline step named Partial Test bench Evaluation (PTE), which "partially evaluates" a test bench by running a pure simulation phase without requiring the hardware accelerator to be connected and generates optimized data to be directly fed into the hardware accelerator. Actual simulation acceleration with a partially evaluated test bench executes much faster than the same with the original test bench.