DocumentCode :
3586230
Title :
A Case for Multi-level Combination of Theorem Proving and Model Checking Tools
Author :
Seidel, Peter-Michael
fYear :
2014
Firstpage :
90
Lastpage :
97
Abstract :
We are combining ACL2 theorem proving with an off-the-shelf commercial model checker to verify a functional unit that would have been hard to verify by just using either of the two approaches. It is essential that our combination of the two tools allows for results of either of the tools to be used for the other tool in both directions. The unit is a packed integer multiplier that can handle a variety of multiplication operations on signed and unsigned integer operands ranging from 8 bits to 32 bits. The implementation of the unit is targeting low-power operation and is described in production RTL. The combination of the two verification approaches builds on the strengths and works around the challenges of each of the two approaches. Communication between the two approaches is based on a standard Veriloginterface. In this manuscript we are describing the verification environment and explain details of the verification project.
Keywords :
formal verification; hardware description languages; low-power electronics; multiplying circuits; theorem proving; ACL2 theorem proving; commercial model checker; functional unit verification; integer operands; low-power operation; multiplication operations; packed integer multiplier; production RTL; signed integer operands; standard Verilog interface; unsigned integer operands; verification environment; verification project; word length 8 bit to 32 bit; Clocks; Engines; Hardware design languages; Libraries; Load modeling; Registers; Wires; ACL2; Model Checking; Multiplication; Theorem Proving; Verilog RTL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microprocessor Test and Verification Workshop (MTV), 2014 15th International
ISSN :
1550-4093
Type :
conf
DOI :
10.1109/MTV.2014.29
Filename :
7087241
Link To Document :
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