A Configurable Random Instruction Sequence (RIS) Tool for Memory Coherence in Multi-processor Systems

The challenge of verification of a multi-processor design is growing rapidly due to the increase of complexity in the design, bus protocols, weakly ordered memory and the presence of multiple hierarchies of caches in the memory subsystem. Adding to this complexity, ARM architecture also defines a set of attributes and characteristics required to support memory and devices in the system memory map. One of the key issues that need to be addressed, under these scenarios, is making sure that memory is consistent and coherent as different processors access, cache and update a single shared address space. In this work we present an ARM internal random instruction sequence (RIS) tool, MEMRIS (Memory Random Instruction Sequence), which provides a scalable approach to verify and validate memory coherence in multi-processor/cluster systems with up to 8-processors in both AARCH32/AARCH64. The output format of the generator is native ARM executables intended to run in a top-level simulation based environment. The MEMRIS generator allows the user to control many aspects of the test such as the number, size and location of address spaces as well as the mix of instructions that will operate on the defined memory regions. These memory regions are then configured to be shared between the Processing Elements (PEs), using defined address constraints, to hence trigger various sharing scenarios and invoke snoops and cache-line migrations. These scenarios are built using assembly sequences bounded into discrete zones. The zones are synchronized with various primitives throughout the test, i.e. Using Bakers algorithm and exclusives. The tool also internally models the code execution threads as to provide an optional self-check memory sequence at the end of the test.