Synthesizable Memory Models for Virtual Prototyping

System development with complex bus architecture requires accuracy to model key system characteristics. It also requires the ability to execute the prototype to examine the behavior of the system for analyzing key metrics. This paper elucidates the development of synthesizable memory models for use in virtual prototyping for enhancing interconnect performance of a SoC and for boot code development. Virtual prototyping provided us with the accuracy, performance, and flexibility to model and analyze complex system to make critical design decisions. Thus, we have successfully modeled the SoC, peripheral memories and board delays, in order to emulate the system behavior. This paper will showcase how we used virtual prototyping for performance validation and early boot code development.