FIES: A Fault Injection Framework for the Evaluation of Self-Tests for COTS-Based Safety-Critical Systems

Safety-critical systems have to satisfy ever-growing demands for high computing performance and cost-efficiency. This leads to a move to commercial off-the-shelf hardware components that are not hardened. Unfortunately, these components are becoming increasingly vulnerable to operational faults and the manufacturers do not guarantee a certain level of dependability. However, in order to maintain a high integrity, safety-critical systems have to ensure the correct functionality of hardware components during operation. Besides redundancy techniques, this is typically realized with build-in self-tests implemented at software level. Safety-standards, such as the IEC 61508 standard, prescribe certain fault models that should be used to assess the diagnostic coverage of self-tests with fault injection experiments. Typical fault injection frameworks use gate-level net lists or RTL models. However, these hardware models are not publicly available for most COTS processors. In this paper we present a Fault Injection framework for the Evaluation of software-based Self-tests (FIES) according to the safety standard IEC 61508. This virtual platform supports widely-used embedded COTS processors, such as ARM cores, and provides feedback about the diagnostic coverage of self-tests in early design stages. It supports the simulation of faults in the control and execution path of an ARM processor and features an extended fault model to simulate memory coupling faults. The applicability of the approach is shown by using it for the evaluation of a memory test.