12.5-Gb/s monolithically integrated optical receiver with CMOS avalanche photodetector

Author

Hyun-Yong Jung ; Jeong-Min Lee ; Jin-Sung Youn ; Woo-Young Choi ; Myung-Jae Lee

Author_Institution

Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

2014

Firstpage

1

Lastpage

2

Abstract

We present a 12.5-Gb/s monolithically integrated optical receiver with CMOS avalanche photodetector (CMOS-APD) realized in 65-nm CMOS technology. The optical detection bandwidth limitation of CMOS-APD due to the carrier transit time is compensated by underdamped TIA. With this optical receiver, 12.5-Gb/s 850-nm optical data are successfully detected with bit-error rate less than 10^-12 at the incident optical power of -2 dBm. The fabricated optical receiver has the core size of 0.24 × 0.1 mm² and its power consumption excluding output buffer is about 13.7 mW with 1.2-V supply voltage.

Keywords

CMOS integrated circuits; avalanche photodiodes; error statistics; integrated optoelectronics; monolithic integrated circuits; optical interconnections; optical receivers; photodetectors; CMOS avalanche photodetector; CMOS technology; CMOS-APD; bit error rate; bit rate 12.5 Gbit/s; carrier transit time; monolithically integrated optical receiver; optical detection bandwidth limitation; optical interconnect technology; size 65 nm; underdamped TIA; wavelength 850 nm; Bandwidth; CMOS integrated circuits; CMOS technology; Inductance; Lead; Optical buffering; Optical receivers; Avalanche photodetectors (APDs); Monolithic integration; Optical interconnects; Optical receiver;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2014 International

Type

conf

DOI

10.1109/ISOCC.2014.7087543

Filename

7087543