Title :
Time-to-digital converter architecture with residue arithmetic and its FPGA implementation
Author :
Congbing Li ; Katoh, Kentaroh ; Junshan Wang ; Shu Wu ; Mohyar, Shaiful Nizam ; Kobayashi, Haruo
Author_Institution :
Div. of Electron. & Inf., Gunma Univ., Kiryu, Japan
Abstract :
This paper describes a time-to-digital converter (TDC) architecuture with residue arithmetic or Chinese Remainder theorem. It can reduce the hardware and power significantly compared to a flash type TDC while keeping comparable performance. Its FPGA implementation and measurement resuts show the effectiveness of our proposed architecture.
Keywords :
field programmable gate arrays; time-digital conversion; Chinese Remainder theorem; FPGA implementation; TDC architecuture; flash-type TDC; hardware reduction; power reduction; residue arithmetic; time-to-digital converter architecture; Field programmable gate arrays; Navigation; Chinese Remainder Theorem; FPGA; Residue; Time to Digital Converter; Timing Measurement;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087552
