DocumentCode
3586273
Title
Digital calibration algorithm for half-unary current-steering DAC for linearity improvement
Author
Mohyar, Shaiful Nizam ; Kobayashi, Haruo
Author_Institution
Div. of Electron. & Inf., Gunma Univ., Kiryu, Japan
fYear
2014
Firstpage
60
Lastpage
61
Abstract
This paper introduces an algorithm called 3-stage current sorting (3S-CS) in half-unary weighted current cells to improve the linearity of a current-steering digital-to-analog converter (DAC). Based our statistical analysis and simulation results, the proposed algorithm improves the DAC static linearity as well as its dynamic performance.
Keywords
calibration; digital-analogue conversion; statistical analysis; 3-stage current sorting; DAC static linearity; digital calibration; digital-to-analog converter; half-unary current-steering DAC; half-unary weighted current cells; linearity improvement; statistical analysis; Area measurement; Calibration; Current measurement; Decoding; Silicon; Standards; Switches; current sorting; current source mismatch; current-steering DAC; half-unary weighted; linearity;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2014 International
Type
conf
DOI
10.1109/ISOCC.2014.7087557
Filename
7087557
Link To Document