DocumentCode :
3586283
Title :
Exploring hybrid SRAM/MRAM L2 NUCA stacked on 3D chip-multiprocessors
Author :
Seunghan Lee ; Kyungsu Kang ; Jongpil Jung ; Chong-Min Kyung
Author_Institution :
Smart Sensor Archit. Lab. (SSAL), KAIST, Daejeon, South Korea
fYear :
2014
Firstpage :
26
Lastpage :
27
Abstract :
Non-volatile magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with conventional SRAM. The use of hybrid memories (e.g., SRAM and MRAM together) can take advantage of the best characteristics that each technology offers. In this paper, we explore the 3D-stacked SRAM/MRAM hybrid L2 cache architecture by using a design-time optimization that determined each bank capacity and a ratio between SRAM and MRAM capacities. Also, this paper proposes a runtime cache management scheme that improves the system performance. Experimental results show that the proposed method yields, on the average, 61% performance improvement in terms of instructions per second (IPS) compared to the conventional SRAM-only L2 cache or MRAM-only L2 cache.
Keywords :
SRAM chips; cache storage; magnetic storage; multiprocessing systems; three-dimensional integrated circuits; 3D chip-multiprocessors; 3D-stacked SRAM/MRAM hybrid L2 cache architecture; bank capacity; design-time optimization; high cell density; high write energy; hybrid SRAM/MRAM L2 NUCA; hybrid memories; long write latency; low leakage power; nonvolatile magnetic RAM; runtime cache management scheme; system performance; Random access memory; 3D IC; design-time optimization; dynamic cache management; hybrid cache;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
Type :
conf
DOI :
10.1109/ISOCC.2014.7087567
Filename :
7087567
Link To Document :
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