Title :
Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs
Author :
Kaushal, Gaurav ; Subramanyam, K. ; Rao, Siva Nageswar ; Vidya, G. ; Ramya, Radhika ; Shaik, Sadulla ; Jeong, H. ; Jung, S.O. ; Vaddi, Ramesh
Author_Institution :
Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET´s device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; MOSFET; energy consumption; power aware computing; system-on-chip; tunnel transistors; FinFET technology; TFET circuit; circuit performance metrics; complementary metal oxide semiconductor; energy consumption; low voltage digital circuit; nanoscale CMOS analog circuit; nanoscale CMOS digital circuit; self-powered wearable SOC; size 20 nm; steep-slope tunnel transistor; system-on-chip; tunnel field effect transistor; ultralow power application; vital sign monitoring; voltage scaling; Benchmark testing; CMOS integrated circuits; CMOS technology; FinFETs; Logic gates; Relays; Voltage control; Energy harvesting; FinFETs; Low voltage digital and analog designs; Self-powered SOCs; Steep-slope Transistors; Tunnel FETs; Ultra-low power;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087570
