DocumentCode
3586310
Title
Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)
Author
Jun-Kai Zhao ; Yi-Wei Chiu ; Shyh-Jye Jou ; Yuan-Hua Chu
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2014
Firstpage
114
Lastpage
115
Abstract
In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.
Keywords
SRAM chips; logic design; macros; power aware computing; PC-DVS scheme; SRAM macro design; frequency 500 kHz; leakage power consumption; low-voltage regime; pulse-controlled dynamic voltage scaling scheme; sub-banks; variation immunity; voltage 0.35 V; voltage 0.5 V; CMOS integrated circuits; CMOS technology; Clocks; Q measurement; Random access memory; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2014 International
Type
conf
DOI
10.1109/ISOCC.2014.7087594
Filename
7087594
Link To Document