Modulo scheduler implementation for VLIW processor

For VLIW processors, compiler must statically schedule instructions since there are no hardware for detecting hazards and reordering instructions at runtime. Thus, instruction scheduling techniques for VLIW processors have critical influence on correct execution and effective utilization of hardware resources. Software pipelining is a popular instruction scheduling technique which enables overlapped execution of successive loop iterations. We implemented modulo scheduler, which is a widely used technique of obtaining software pipelined schedule. Experiments on a set of multimedia applications show that performance is increased up to 2.6x compared to simple list scheduling implementation.