Allocation and optimization of Post-silicon tunable buffers in TSV based heterogeneous 3D ICs

Through-silicon via (TSV) based 3D IC design is a promising solution to reducing the length of interconnects and improving the power and speed. However, when heterogeneous dies are stacked together to form a 3D IC, a considerable timing discrepancy among the layers could happen since the devices in different layers might have been affected quite differently by process variations. With this respect, this work makes two contributions: (1) proposing a PST buffer allocation scheme in 3D ICs to resolve the timing discrepancy between dies; (2) with the proposed allocation scheme, proposing a technique that is able to minimize the total cost of PST buffer implementation.