Title :
A digital lock detector for a dual loop PLL
Author :
Chang-Hyun Bae ; Changsik Yoo
Author_Institution :
RAM Design, Samsung Electron., Hwaseong, South Korea
Abstract :
A digital lock detector capable of detecting frequency variations occurred during the operation of a digital filter of the detector is proposed. In this paper, the digital lock detector is applied to a dual loop PLL to give the frequency lock information to another PLL loop. The proposed lock detector with the PLL fabricated in a 0.13-μm CMOS process occupies 0.17-mm2 and consumes 35-mW from a 1.2-V power supply. The measured frequency offset between two VCOs is 0.16-%.
Keywords :
CMOS digital integrated circuits; digital filters; digital phase locked loops; CMOS process; VCO; digital filter; digital lock detector; dual loop PLL; frequency lock information; frequency offset; frequency variation detection; power 35 mW; size 0.13 mum; voltage 1.2 V; voltage-controlled oscillators; Delays; Logic gates; Phase locked loops; Velocity measurement; CMOS; Lock Detector; PLL;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087610
