Implementation of efficient SHA-256 hash algorithm for secure vehicle communication using FPGA

Author

Chanbok Jeong ; Youngmin Kim

Author_Institution

Sch. of Electr. & Comput. Eng., Ulsan Nat. Inst. of Sci. & Technol. (UNIST), Ulsan, South Korea

fYear

2014

Firstpage

224

Lastpage

225

Abstract

In this paper, we implement the SHA-256 FPGA hardware module for the security protocol of the IEEE 1609.2 vehicle communication (VC). VC requires high-throughput and low-latency hardware architectures. For fast and efficient design, we exploit parallel structures for preprocessing and hash computation in SHA-256. The proposed design is im- plemented in Vertex-5 and verified for correct hash operation. As a result, we can achieve up to 179.08 MHz with 2796 slices.

Keywords

cryptography; field programmable gate arrays; parallel processing; IEEE 1609.2 vehicle communication; SHA-256 FPGA hardware module; SHA-256 hash algorithm; VC; Vertex-5; correct hash operation; hash computation; parallel structures; secure vehicle communication; security protocol; Adders; Documentation; Field programmable gate arrays; Software; Standards; FIPS-180-3; FPGA; Hash Algorithm; IEEE 1609.2; SHA-256; Security for Vehicle Communication;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2014 International

Type

conf

DOI

10.1109/ISOCC.2014.7087617

Filename

7087617

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3586333