DocumentCode :
3586392
Title :
A high speed pipeline structure of hardware implementation for block classification for distributed video coding
Author :
Qiang Tong ; Ken Choi
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fYear :
2014
Firstpage :
160
Lastpage :
162
Abstract :
Distributed video coding (DVC) is a video coding paradigm that aims at shifting the complexity from the encoder to the decoder. Traditionally, the existing DVC codecs encode the video frames as either key frame or Wyner-Ziv (WZ) frame. In WZ frames, all blocks are encoded as WZ blocks. We observed that, in WZ frame, there exists few blocks having intense motions, while many blocks have scarce motions. To improve the higher Rate-Distortion performance, we need to classify the blocks in a WZ frame into three categories, namely key block, WZ block and skip block. And encode each category with different scheme. So, a high speed classifier is very important to improve the throughput of the codec. In this paper, we propose a high speed pipelined block classifier for distributed video codec, which is suitable to work in real time video processing.
Keywords :
image classification; pipeline processing; rate distortion theory; video codecs; video coding; DVC codecs; WZ blocks; WZ frame; Wyner-Ziv frame; distributed video codec; distributed video coding; hardware implementation; high speed pipeline structure; key frame; pipelined block classifier; rate distortion performance; real time video processing; throughput improvement; video frame encoder; Codecs; Digital signal processing; Block Classification; Distributed Video Coding (DVC); High Speed Circuits; Pipelining; Very Large Scale Integrated (VLSI) Circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
Type :
conf
DOI :
10.1109/ISOCC.2014.7087676
Filename :
7087676
Link To Document :
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