Title :
TAB-model for multilevel diagnosis and repair of HDL SoC
Author :
Hahanov, Vladimir ; Ka Lok Man ; Abbas, Baghdadi Ammar Awni ; Litvinova, Eugenia ; Chumachenko, Svetlana ; Jihyeok Ahn ; Kyung Ki Kim
Author_Institution :
Nat. Univ. of Radioelectron., Kharkov, Ukraine
Abstract :
This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.
Keywords :
fault diagnosis; graph theory; hardware description languages; matrix algebra; system-on-chip; HDL SoC repair; TAB-model; activation matrix; diagnosis matrix storage; embedded hardware fault diagnosis; fault detection; faulty block detection; multilevel diagnosis method; synthesis logic functions; transaction graph; Computers; Software; Standards; HDL SoC model; diagnosis; faulty blocks detection; transaction graph;
Conference_Titel :
SoC Design Conference (ISOCC), 2014 International
DOI :
10.1109/ISOCC.2014.7087686
