A review on system level low power techniques

With the shrinking integrated circuits (IC) technology and the popularity of portable electronic devices, power dissipation has become a critical issue in very large scale integrated (VLSI) circuits design. To reduce the power dissipation, much attention had been drawn to the techniques in process technology, circuits level, gates level and register-transfer (RT) level. However, from the experience with the traditional approach, it is clear that system level design optimization have the greatest influence on power consumption. And hence, power optimization techniques in system level are able to gain considerable power reduction, compared with techniques in other level. In this review, some general state-of-art system-level low power techniques are tested and reviewed, and some guidelines for system level low power design are generalized.