Title :
The hardware design of LDPC decoder in IEEE 802.11n/ac
Author :
Hyobeen Park ; Seongjoo Lee
Author_Institution :
Dept. of Inf. & Commun. Eng., Sejong Univ., Seoul, South Korea
Abstract :
In this paper, the design of the LDPC decoder architecture in IEEE 802.11n/ac is proposed. The proposed decoder is used to the partial parallel architecture to provide 2 Gbps throughput at 200 MHz clock frequency. In IEEE 802.11n/ac, 12 parity check metrics is provide to support diverse code rates and block lengths. Therefore the network between nodes is configured to be satisfied parity check metrics. However, the structure of the network increases the complexity of LDPC decoder. Hence, the optimized network generator is also proposed to reduce the complexity of the network.
Keywords :
decoding; parity check codes; wireless LAN; IEEE 802.11n-ac; LDPC decoder architecture; bit rate 2 Gbit/s; block lengths; diverse code rates; frequency 200 MHz; hardware design; network generator optimization; parity check metrics; partial parallel architecture; Complexity theory; Decoding; IEEE 802.11n Standard; Measurement; Parallel architectures; Parity check codes; IEEE 802.11n/ac; LDPC decoder; optimized network; quasi-cyclic low-density parity-check code;
Conference_Titel :
Electronics, Computers and Artificial Intelligence (ECAI), 2014 6th International Conference on
Print_ISBN :
978-1-4799-5478-0
DOI :
10.1109/ECAI.2014.7090144
