A micro-architecture design for the 32-bit VLIW DSP processor core

Digital signal processing plays an important role in human life nowadays with various applications such as speech recognition, medical imaging, oil prospecting, etc. However, those applications cannot achieve high performance in general-purpose processors due to specific digital signal processing algorithms including Fourier transform, digital filtering, etc. Hence, the emergence of digital signal processors (DSPs) can be considered as urgent and timely solution as the strong optimizations of their architectures aim at maximizing the performance of those applications. In this work, we present a micro-architecture design of the 32-bit VLIW DSP Processor core based on the proposed top-level architecture and instruction set architecture in our previous work. This micro-architecture is then implemented by using the Verilog HDL and simulated in Altera ModelSim tool.