A methodology of fault detection using design for testability of CP-PLL

Charge-pump phase-locked loop (CP-PLL) is one of RF circuits, which is widely used to generate timing or reference signals in communication systems, needs to be verified correctly. This paper proposes a low-cost design-for-testability (DFT) structure for a classical CP-PLL circuit to allow simple digital testing. The proposed DFT structure uses the existing circuit units as one part of test device in the test mode. It can be easily implemented with several logic gates. The test circuit is all digital. It avoids the need of interfacing any foreign component and decreases the test cost of whole IC. Moreover, the proposed structure only needs a minor modification of the digital part in CP-PLL avoiding the loading effect at analog node. Fault simulation results indicate that the proposed structure posses high fault coverage of 98.33%. Thus it provides an efficient structural fault test for CP-PLL.