Design and analysis of source coupled logic circuits

Author

Varma, Raghvendra Pratap ; Chandel, Rajeevan

Author_Institution

Electron. & Commun. Dept., Nat. Inst. of Technol., Hamirpur, India

fYear

2014

Firstpage

1

Lastpage

6

Abstract

In this paper, full adder circuits are implemented in pass transistor, CMOS and Source Coupled Logic and analyzed. SCL circuit is further minimized using multiplexer minimization technique and provides to an enhanced performance. Delay, power dissipation, number of transistors, current spike and their product are considered the performance metrics for the present analysis. Of the various adders implemented, SCL full adder circuit provides minimum current spike between power supply (V_DD) to ground during state transition and best figure of merit. This makes SCL logic noise immune, rugged and an excellent candidate for mixed mode circuit design. Simulations are performed using Tanner EDA Tools for 0.18μm technology node.

Keywords

CMOS logic circuits; adders; coupled circuits; CMOS; SCL full adder circuit; full adder circuits; mixed mode circuit design; multiplexer minimization technique; pass transistor; power supply; source coupled logic circuits; state transition; Adders; CMOS integrated circuits; Logic gates; MOS devices; Multiplexing; Threshold voltage; Transistors; CMOS logic; Full adder circuits; Pass transistor logic; SCL;

fLanguage

English

Publisher

ieee

Conference_Titel

Convergence of Technology (I2CT), 2014 International Conference for

Print_ISBN

978-1-4799-3758-5

Type

conf

DOI

10.1109/I2CT.2014.7092217

Filename

7092217