An energy-efficient two-level cache architecture for chip multiprocessors

As microprocessors begin to leverage multi-core functionality, the power consumption incurred from tag comparison in cache hierarchy of Chip Multi-Processors (CMPs) becomes more prevalent. In this paper, a novel two-level cache architecture is explored to reduce the tag comparisons for mitigating power overhead. For one thing, a way-tagged L1 cache is adopted to access the L2 cache as a direct-mapping manner during the write hits. Moreover a combined multistep method is used to further reduce the L2 tag comparisons for both cache hit and miss predictions. With a simple predictor and the coherence status, a new prediction scheme for backward invalidation is proposed to compensate the limitation of the two applied solutions in CMPs. Furthermore, for the realization and optimization of the proposed structure, a banked Bloom Filter and a Linear Feedback Shift Register (LFSR) counter are exploited to replace the traditional predictors. Simulation results show that, the proposed technique can reduce the total cache power by an average 49.7% at the cost of the acceptable performance overhead.