Title :
A reduced-complexity iterative scheme for decoding quasi-cyclic low-density parity-check codes
Author :
Shu Lin ; Keke Liu ; Juane Li ; Abdel-Ghaffar, Khaled
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA
Abstract :
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.
Keywords :
computational complexity; cyclic codes; iterative decoding; matrix algebra; parity check codes; QC-LDPC code decoder; descendant QC-LDPC codes; hardware implementation complexity reduction; high-rate high-performance QC-LDPC code; message processing units; parity-check matrices; quasicyclic low-density parity-check codes; reduced-complexity iterative decoding scheme; section-wise cyclic structure; wires; Arrays; Complexity theory; Decoding; Iterative decoding; Null space; Reliability; Wires;
Conference_Titel :
Signals, Systems and Computers, 2014 48th Asilomar Conference on
Print_ISBN :
978-1-4799-8295-0
DOI :
10.1109/ACSSC.2014.7094410