Title :
A systematic procedure for deriving block-parallel, power efficient, digital filter architectures for highspeed data conversion
Author :
Argyropoulos, Paraskevas ; Lev-Ari, Hanoch
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
A systematic and highly intuitive procedure for deriving the digital filter realization of an arbitrary block-parallel and/or pipelined discrete-time transfer function H(z) is proposed. The method is based on simple block diagram and multi-rate (filter-bank) properties and is intended for low-power processing by reducing (a) the required system clock frequency and (b) the number of required multipliers by facilitating arithmetic resource sharing. We provide design examples for (classical) direct-form FIR and IIR filters as well as for specialized architectures such as fractional-delay Farrow (programmable FIR), lattice-ladder (IIR), Adaptive Phase Equalization (programmable IIR) and Multiplier-less MAXFLAT filters. The technique and examples presented are intended to serve as a high-speed filter realization reference for Digital and DSP ASIC developers.
Keywords :
FIR filters; IIR filters; data conversion; discrete time filters; pipeline arithmetic; resource allocation; transfer functions; DSP ASIC developers; arithmetic resource sharing; block-parallel architecture; clock frequency; digital filter architecture; direct-form FIR filters; direct-form IIR filters; filter-bank properties; high-speed data conversion; low-power processing; multirate properties; pipelined discrete time transfer function; power efficient architecture; Clocks; Decision support systems; Digital signal processing; Finite impulse response filters; IIR filters; Systematics; Block-Parallel Digital Filter; Farrow Filter; Low Power Filter Design; Pipelined Digital Filter; Polyphase Decomposition;
Conference_Titel :
Signals, Systems and Computers, 2014 48th Asilomar Conference on
Print_ISBN :
978-1-4799-8295-0
DOI :
10.1109/ACSSC.2014.7094507
