Low-power radix-4 quotient generator

A study of low-power radix-4 quotient generators is presented. A modified SRT division algorithm [2] is used to produce the quotient but not the final remainder. Consequently, a gradual bit-slice deactivation (i.e., progressive truncation of the residual precision) is exploited to reduce the number of active modules across iterations and, consequently, to reduce power dissipation and energy. An increasing portion of the divider circuit area turns into “dark silicon”. In this paper we report preliminary synthesis results of radix-4 quotient generators for 16, 24, 32, and 54 bits with respect to area, delay, power dissipation, and energy. We compare these results with the corresponding results of conventional full-precision radix-4 SRT dividers for the same cases. The results indicate a potential for significant reduction of power dissipation and energy but no effect on latency.