Title :
Dynamically reconfigurable multi-processor arrays
Author :
Glenn-Anderson, James
Author_Institution :
Supercomput. Syst., Inc., Las Vegas, NV, USA
Abstract :
In this paper, the FPGA-based Multi-Processor Array architectural form is augmented with capability for hardware partial reconfiguration on processor element I/D-space memory components. Reconfiguration overhead is effectively masked on the process schedule timeline with use of an associated pipelining mechanism. In this manner, a maximally-parallel processing gain may be achieved. The resulting structure is then leveraged in support of a spatiotemporal processing model applicable to arbitrarily large dataflow graphs.
Keywords :
data flow graphs; field programmable gate arrays; multiprocessing systems; parallel architectures; pipeline processing; processor scheduling; reconfigurable architectures; spatiotemporal phenomena; FPGA-based multiprocessor array architectural form; associated pipelining mechanism; dataflow graph; dynamically reconfigurable multiprocessor array; hardware partial reconfiguration; maximally parallel processing gain; process schedule timeline; processor element I/D space memory component; reconfiguration overhead; spatiotemporal processing model; Arrays; Decision support systems; Field programmable gate arrays; Indexes; Pipeline processing; Spatiotemporal phenomena; System-on-chip; FPGA; SCoC; SoC; dataflow supercomputing; dynamic reconfiguration; embedded supercomputing; multi-core processor; multiprocessor array; parallel processor; partial reconfiguration; spatiotemporal reconfiguration;
Conference_Titel :
Signals, Systems and Computers, 2014 48th Asilomar Conference on
Print_ISBN :
978-1-4799-8295-0
DOI :
10.1109/ACSSC.2014.7094790
