DocumentCode :
3588077
Title :
Noisy belief propagation decoder
Author :
Chu-Hsiang Huang ; Yao Li ; Dolecek, Lara
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Los Angeles, Los Angeles, CA, USA
fYear :
2014
Firstpage :
2111
Lastpage :
2115
Abstract :
This paper analyzes the fundamental performance limits of an LDPC Belief Propagation (BP) decoder implemented on noisy hardware and proposes a robust decoder implementation to improve the resilience to hardware errors. Assuming that the effects of hardware noise in various computational units, i.e., variable nodes and check nodes, can be approximated by Gaussian noise, we develop a Gaussian approximate density evolution for noisy BP decoders. By the Gaussian approximate density evolution, we find that zero residual error rate is achievable for noisy BP decoders as long as the message representations are of arbitrarily high precision. Noisy BP decoding thresholds are then derived for various regular LDPC codes. These decoding thresholds determine maximum allowable communication and computation noise for reliable communication. Next, we propose an averaging BP decoder implementation by averaging over the messages in all up-to-date iterations to cancel out the computation noise. Simulation results demonstrate that on noisy hardware, the averaging BP decoder significantly reduces the residual error rates when compared to the nominal BP decoder.
Keywords :
Gaussian noise; decoding; parity check codes; Gaussian approximate density evolution; Gaussian noise; LDPC BP decoder; LDPC belief propagation decoder; averaging BP decoder implementation; check nodes; computation noise; computational units; fundamental performance limits; hardware error resilience improvement; hardware noise; maximum allowable communication; message representations; noisy BP decoders; noisy BP decoding thresholds; noisy belief propagation decoder; noisy hardware; residual error rate reduction; robust decoder implementation; variable nodes; zero residual error rate; Computational modeling; Decoding; Error analysis; Hardware; Noise; Noise measurement; Parity check codes; Algorithm and Architecture Co-optimization (G.5); Coding and Decoding (A.2); Review Topic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 2014 48th Asilomar Conference on
Print_ISBN :
978-1-4799-8295-0
Type :
conf
DOI :
10.1109/ACSSC.2014.7094847
Filename :
7094847
Link To Document :
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