DocumentCode :
3588087
Title :
Development and optimization of high level dataflow programs: The HEVC decoder design case
Author :
Jerbi, Khaled ; Renzi, Daniele ; De Saint Jorre, Damien ; Yviquel, Herve ; Raulet, Mickael ; Alberti, Claudio ; Mattavelli, Marco
Author_Institution :
IETR, INSA Rennes, Rennes, France
fYear :
2014
Firstpage :
2155
Lastpage :
2159
Abstract :
With the standardization of the new High Efficiency Video Coding (HEVC) compression algorithm, a dataflow specification of the HEVC decoding process is also available as part of the standard. This paper presents methodologies to improve and optimize the performance of implementations derived by the dataflow specification. Regarding the architectural aspect of dataflow network, the throughput has been increased by developing more potential parallelism. For the platform aspect, critical processes have been optimized by applying SIMD functions and communications have been improved by cache efficient FIFO implementation. Results revealed an average acceleration factor of 7 in the decoding framerate over the reference dataflow implementation.
Keywords :
cache storage; data flow analysis; formal specification; parallel processing; video coding; HEVC decoding process; SIMD functions; average acceleration factor; cache efficient FIFO implementation; dataflow network; dataflow specification; decoding framerate; high efficiency video coding compression algorithm; performance improvement; performance optimization; reference dataflow implementation; Decoding; Kernel; Libraries; Optimization; Parallel processing; Standards; Video coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 2014 48th Asilomar Conference on
Print_ISBN :
978-1-4799-8295-0
Type :
conf
DOI :
10.1109/ACSSC.2014.7094857
Filename :
7094857
Link To Document :
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