A compact PCI-based measurement and control system for satellite-ground quantum communication

Summary form only given. Since the 1990s, there has been a dramatic interest in quantum communication. Quantum communication has become the hotspot of future information technology research because of its unique advantages in improving the security, capability and efficiency of information transmission. Free space quantum communication is being developed to ultra-long-distance satelliteto-ground quantum experiment, which requires higher electronics performance, such as time measurement precision, data transfer rate, and system integration density. As part of ground station of scientific applications system of quantum experiment satellite that will be launched in 2016, a compact PCI-based multi-channel electronics system with high timeresolution, high data-transfer-rate is designed. The main tasks of this system are time measurement, data transmission and experiment control. Based on the compact PCI system, we designed the following functions in a standard 6U size circuit board. A 16-channel high resolution time-to-digital converter (TDC), using the field-programmable-gate-array´s (FPGA´s) carry chains, is implemented to detect and record the arrival time of the input signals. The TDC is based on a counter and an interpolator method. Taking full advantage of the FPGA´s flexibility, not only the above, but also some necessary modules in the quantum communication experiment such as multi-channel counter, system monitor and experiment control logic are integrated in a single FPGA. The system monitor module is used to measure the voltage and current on board, and FPGA temperature. A GPS signal is used to synchronize clocks over large distance with high precision and accuracy. A physical random generator provides enough random numbers by before the start of communication and stores them in a local memory. A synchronous dynamic random access memory (SDRAM) is used to guarantee no data loss during processing. The data transmission is based on compact peripheral componen- interconnect (CPCI) to guarantee a high data rate. A complex programmable logic device (CPLD) functions as the interface with the IP core between the FPGA and the PCI bus, and configures the FPGA online via PC.