Design of Giga bit Ethernet readout module based on ZYNQ for HPGe

ZYNQ is the new all programmable SoC architecture of FPGA with dual-core high performance ARM Cortex-A9 processors from Xilinx. A new module with Giga-bit Ethernet interface based on the ZYNQ XC7Z010 is development for the High Purity Germanium Detectors´ data acquisition in the CJPL (China JingPing under-ground Lab) experiment. With the new architecture of ZYNQ, the embedded open source Linux with TCP/IP stack and the real time high throughput logic based on VHDL can be combined to run in a single ARM + FPGA chip with lower profile, lower power and highest performance. It´s very differently from the classic architecture with two chips, one processor plus one FPGA. This paper will introduce how about the architecture of the readout module and how the new module can archive higher performance than the classic one. Also the throughput of the Giga-bit Ethernet which more than 500Mbps will be introduce and a verify platform of HPGe data acquisition system based on the new module will also be introduced.