• DocumentCode
    3588601
  • Title

    FPGA based control and data acquisition interfaces for PANDA components

  • Author

    Drochner, M. ; Kleines, H. ; Waasen, S.V.

  • Author_Institution
    ZEA-2, FZ Julich, Julich, Germany
  • fYear
    2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    For the upcoming PANDA detector at FAIR (Darmstadt, Germany), various components for timing distribution, control and data acquisition are being constructed. Design objective is to support testing of detector components in a laboratory environment, while keeping it scalable and use hardware platforms and interfaces already agreed on for the final implementation.
  • Keywords
    data acquisition; field programmable gate arrays; forward error correction; nuclear electronics; physical instrumentation control; position sensitive particle detectors; protocols; readout electronics; AMC module; CERN GBT platform; DESY; FAIR; FPGA; KIT; MicroTCA.4; PANDA detector; SODANET protocol; anti-proton annihilation at Darmstadt; data acquisition interfaces; data transfer; forward error correction; link clock; serial links; synchonous mode; unidirectional link; Data acquisition; Detectors; Field programmable gate arrays; Protocols; Synchronization; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real Time Conference (RT), 2014 19th IEEE-NPSS
  • Print_ISBN
    978-1-4799-3658-8
  • Type

    conf

  • DOI
    10.1109/RTC.2014.7097558
  • Filename
    7097558
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3588601