DocumentCode :
3588604
Title :
A new DMA PCIe architecture for Gigabyte data transmission
Author :
Rota, L. ; Caselle, M. ; Chilingaryan, S. ; Kopmann, A. ; Weber, M.
Author_Institution :
Inst. fur Prozessdatenverarbeitung und Elektron. (IPE), Karlsruhe Inst. of Technol. (KIT), Eggenstein-Leopoldshafen, Germany
fYear :
2014
Firstpage :
1
Lastpage :
2
Abstract :
PCI Express (PCIe) is a high-speed serial point-to-point interconnect that delivers high-performance data throughput. KIT has developed a Direct Memory Access (DMA) engine compatible with the Xilinx PCIe core to provide a smart and low-occupancy alternative logic to expensive commercial solutions. In order to maximize the PCIe throughput the DMA engine adopts a new strategy, where the DMA descriptor list is stored inside the FPGA and not in the central memory system. The FPGA design package is complemented with a simple register access to control the DMA engine by a Linux driver. A handshaking sequence between the DMA engine and the Linux driver ensures that no errors occure, even in data transfers of several hundreds of Gigabytes. The design has been tested with Xilinx FPGA Families 6 and 7, and operates with the Xilinx PCIe endpoint generation 1 and 2 with all lane configurations (x1, x2, x4, x8, x16). Data throughput of more than 3.4 GB/s has been achieved with a PCIe Gen 2 ×8 lanes endpoint. The proposed DMA is currently used in several experiments at the ANKA synchrotron light source.
Keywords :
Linux; device drivers; field programmable gate arrays; file organisation; logic design; peripheral interfaces; ANKA synchrotron light source; DMA PCIe architecture; DMA descriptor list; FPGA design package; Linux driver; PCI express; Xilinx FPGA families 6; Xilinx FPGA families 7; Xilinx PCIe core; Xilinx PCIe endpoint generation 1; Xilinx PCIe endpoint generation 2; direct memory access engine; gigabyte data transmission; high-performance data throughput; high-speed serial point-to-point interconnect; lane configurations; low-occupancy alternative logic; register access; smart alternative logic; Data acquisition; Data transfer; Engines; Field programmable gate arrays; Graphics processing units; Linux; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Real Time Conference (RT), 2014 19th IEEE-NPSS
Print_ISBN :
978-1-4799-3658-8
Type :
conf
DOI :
10.1109/RTC.2014.7097561
Filename :
7097561
Link To Document :
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