Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs

Clock Distribution Networks (CDN) in three dimensional ICs face problems due to temperature and gradients observed across the die. The propagation delay of paths in the CDN varies and leads to mismatch in skew at the distribution points. This could potentially harm the system by violating setup and hold timing constraints. Compensation techniques can however be integrated with the CDN to compensate for the effects due to thermal gradients. Two such techniques called adaptive supply voltage and controllable path delay were implemented and are presented in this paper. An FPGA-based test vehicle was used to validate these techniques. Finally the overhead of area and power is analyzed and the performance improvement is observed.