Discrete-time modeling and simulation considerations for high-speed serial links

Modeling and simulation methodologies are presented which are applicable to two critical components of a high-speed serial link, namely phase-locked loop (PLL) and clock and data recovery (CDR) blocks. Specifically, modeling techniques for two nonlinear parameters of a digital CDR (or PLL) is discussed. First, a statistical method is presented to calculate the bang bang phase detector gain in presence of link nonidealities such as random jitter, sinusoidal jitter, and inter symbol interference. Second, a time-domain simulation approach is introduced for calculating the gain of the decimation filter. The accuracy of these two methods are evaluated by comparing the jitter tolerance and jitter transfer of CDR, calculated using the linearized model of CDR, versus those extracted from time-domain simulation of the nonlinear CDR model.