Title :
Effectiveness analysis of de-embedding method for typical TSV pairs in a silicon interposer
Author :
Qian Wang ; Shringarpure, Ketan ; Bichen Chen ; Jun Fan ; Chulsoon Hwang ; Siming Pan ; Achkir, Brice
Author_Institution :
EMC Lab., Missouri Univ. of Sci. & Technol., Rolla, MO, USA
Abstract :
In this paper, a de-embedding method to extract the performance of a Through-Silicon-Via (TSV) pair is proposed, using a set of specially designed test patterns to remove the pads and connection trace. Considering in real implementations, wafer probe measurements are required to access the test structures, and any errors in the probe calibration affect the test pattern measurements, a micro-probe model is built in with the test. Short-Open-Load (SOL) calibration method is used with the simulation results to calibrate or correct to the tips of the micro-probe used in all test patterns. Calibrated responses for the test patterns consisting of probing pads, traces and TSV pair, thus are used with previously proposed de-embedding algorithm to characterize the TSV pair. The effectiveness and the robustness of the de-embedding method against probe calibration errors are tested with the full wave simulation results and analytical calculations.
Keywords :
calibration; elemental semiconductors; integrated circuit testing; silicon; three-dimensional integrated circuits; TSV; analytical calculations; de-embedding method; effectiveness analysis; full wave simulation; micro-probe model; probe calibration affect; probe calibration errors; short-open-load calibration; silicon interposer; test pattern measurements; through-silicon-via; wafer probe measurements; Calibration; Impedance; Probes; Reflection coefficient; Silicon; Standards; Through-silicon vias; SOL calibration; TSV; analytical; calibration patterns; de-embedded; full wave simulation;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2014 IEEE 23rd Conference on
Print_ISBN :
978-1-4799-3641-0
DOI :
10.1109/EPEPS.2014.7103643